1. Field of the Invention
The present invention relates to an integrated circuit provided with a nonvolatile data storage circuit in a multi-threshold-voltage CMOS for enabling low power consumption, and more particularly to an integrated circuit which is capable of simplifying a power supply layout and avoiding erroneous operations during a data recall operation.
2. Description of the Related Art
A multi-threshold-voltage CMOS (MTCMOS) has been proposed as technology for reducing power consumption in an LSI (large-scale integrated circuit). According to this MTCMOS technology, as described in non-patent document 1, for example, which will be described herein below, the high current driving capability of a low-Vth transistor and the low leakage quality of a high-Vth transistor are used to enable high-speed operations and low power consumption. For example, high-speed operations are enabled by constructing a combinational logic circuit having a predetermined function with a low-Vth transistor. In the low-Vth transistor, however, leakage current is generated during standby period or sleep mode period (to be referred to as “sleep mode” hereinafter), leading to an increase in power consumption. Hence an artificial power supply line (virtual power supply line) connected to a high power supply VDD or low power supply VSS via a sleep switch is provided and the combinational logic circuit is connected to this artificial power supply line such that during sleep mode, leakage current is suppressed by switching the sleep switch off. The sleep switch is constituted by a high-Vth transistor, and thus the generation of leakage current when the sleep switch is off can be suppressed.
Hence according to MTCMOS technology, leakage current can be suppressed by switching off the sleep switches of a part of or all of the circuits during sleep mode. Since no power supply voltage is supplied, however, a problem arises in that the data held in the latches and flip-flops inside the circuit become volatile.
As a technique for solving this problem, a balloon-type data holding circuit has been proposed. An MTCMOS circuit having a balloon-type data holding circuit is disclosed in non-patent document 1, for example, which will be described hereinafter, and is as shown in the circuit diagram of a conventional example in FIG. 1. In this example, a combinational circuit 1 and a latch circuit 2 are constituted by low-Vth transistors and are capable of high-speed operations. A virtual power supply voltage VVdd which is connected to a normal power supply voltage Vdd via a sleep switch SSW is connected to these circuits 1, 2. The sleep switch SSW is constituted with a high-Vth, and in sleep mode enters a non-conducting state due to the L level of a sleep control signal SLP, thus suppressing leakage current in the combinational circuit 1 and latch circuit 2.
The data held in the latch circuit 2 should desirably be nonvolatile even in sleep mode. Thus, a balloon latch circuit 3 is connected to the latch circuit 2 such that when switching from active mode to sleep mode, the data held in the latch circuit 2 are sheltered or evacuated inside the balloon latch circuit 3. Since the normal power supply voltage Vdd is connected to the balloon latch circuit 3, power supply voltage is supplied to the latch circuit 3 even in sleep mode, and thus the sheltered data can be held. In order to suppress leakage current during sleep mode, the balloon latch circuit 3 is also constituted by a high-Vth transistor. When sleep mode returns to active mode, the data in the balloon latch circuit 3 are restored to the latch circuit 2. As a result, the latch circuit 2 becomes a nonvolatile latch circuit.